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Re: Re: Rep:Re: [f-cpu] register set, latches



hi !

>> once you have designed the dual-edge cell, you can reuse it instead
>> of the standard cell. The problem might come from static timing analysis
>> but the effect is that it will return an operating frequency that is
>> 2x that of the real frequeny.
>
>I'm little lost, what is going to be the design methodology with FCPU for
>ASIC. Is it full manual layout and GDSII signoff or standard cell based
>technology and possibility for netlist signoffs. There is no way you can
>get your own cells to vendor libraries without big amounts of money (and
>timeframes are long for new cells). And how about dual-edge cells in FPGAs
>etc.

The dual-edge thing is obviously "technology-dependent".
It can be possible to simulate it easily in VHDL and even make a cell
for it with existing cells (take 3 muxes and 2 inverters).

But let me state is clearly ! this is independent from the F-CPU
or any known implementation. I even do believe that such
cells exist for some "custom" designs such as for the P4
and might be a problem for the patents. BUT i know that
in theory it is possible. I'm such an "itch scratcher"...

>If the flow is done from the start to the end the tools are astronomically
>expensive, synthesizers are cheap compared to tools needed for layout
>(library compilers, layout tools, memory compilers etc.). Also for manual
>layout all PLLs etc. need to be designed and characterized for the
>process.Count few rounds of silicon just for cell testing to verify the
>own cell library,

I am aware... Even though they don't say that, in our courses in the university ;-)

>My advise is to use standard cells and nothing too fancy. Many vendors
>have many exotic cells available, but they are not very portable (4- and
>8-port memories, special register banks, CAM, special I/O, 1T-SRAM, eDRAM
>etc.)

my problem now is to have a generic interface for them.
Is there a public library of portable cells ?

>--Kim
YG

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