Re: Re: [f-cpu] No latches, please !

[whygee@club-internet.fr]

The latches nightmare continues here ;-P
Don't read if you're easily technically offended


>On Wed, 13 Feb 2002, Ben Franchuk wrote:
>> nicolas.boulay@ifrance.com wrote:
>> > 
>> > I have miss that : please NO LATCH in our design !!!!
>> > 
>> > It's almost useless compare to classique flip-flop. I
>> > have said nothing for the register set because of the
>> > speed. But latch are generaly a very very bad idea.
>> > It's almost impossible to test correctly and a lot of
>> > tools have problem with them (static timing analysis,
>> > compiler ...).
>> > 
>> Time for better tools? Latches have their place in design, but require
>> more care with design and clock generation. 
>
>Usually you only use latches to synchonize input signals
>to keep input setup times of other circuitry.

<start delirious block>

If we were SURE that the number of pipeline stages was EVEN,
we could do something really... CRAZY !

Remember : a FlipFlop is a pair of transparent latches
that are activated with an opposite signal. Under the following
conditions :
 - setup/hold times respected (more difficult because of the distance
    and phase shift/delay)
 - even number of stages
it would be possible to use only latches in a pipeline...

<end delirious block>

<standard_disclaimer>
The above is only pure speculation. I know some people will
like while others will love it. It's funny but is not part of the F-CPU project.
<standard_disclaimer>

have fun,

>JG
YG

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