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Re: Rep:Re: Re: [f-cpu] No latches, please !



Some example :
http://www.cse.psu.edu/~cg577/hw1s98.html



nicO a écrit :
> 
> Ben Franchuk a écrit :
> >
> > nicolas.boulay@ifrance.com wrote:
> > >
> > > That's not crazy it's called multiphased logic. You
> > > could use 2 or 4 clock phased to synchronise things
> > > but i imagine what a nightmarre it could be to debug
> > > and to test.
> > >
> > But it has two advantages ... 1) A latch is quicker than
> > a flip/flop. 2) You need less clock buffering.
> >
> 
> 1) it's the only advantage over all the disadvantage.
> 
> 2) depend completly of the design of the latch !! And in the common
> case, false !
> 
> You could find flip-flop with the clock connected to 1 to many
> transistor gate !
> 
> nicO
> 
> > --
> > Ben Franchuk - Dawn * 12/24 bit cpu *
> > www.jetnet.ab.ca/users/bfranchuk/index.html
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