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Re: Rep:Re: Re: [f-cpu] No latches, please !



hello,

Michael Riepe wrote:
> On Thu, Feb 14, 2002 at 10:20:16AM -0700, Ben Franchuk wrote:
> > nicolas.boulay@ifrance.com wrote:
> > >
> > > That's not crazy it's called multiphased logic. You
> > > could use 2 or 4 clock phased to synchronise things
> > > but i imagine what a nightmarre it could be to debug
> > > and to test.
> > >
> > But it has two advantages ... 1) A latch is quicker than
> > a flip/flop. 2) You need less clock buffering.
> 
> A latch is quicker in terms of what? Delay time? Setup time? Clock
> frequency?

first, it's a bit smaller. Depending on the amount of control logic,
the gain varies. The memory cell (4 transistors) requires decoding
and clock buffering, IIRC the sxlib FF uses around 20 transistors.

Setup time + hold are the same or not, depending on the kind
of gates you use. For example, in sxlib, they use a couple of 4T cells
which are overwritten by using a buffer with high driving capability.
On of the inverters of the 4T cell has a low drive and the buffer can
overwrite the previous value.
I guess that because there is no problem of clock and transmitting
the data from one latch to another, the setup+hold requirements
disappear (but certainly arise in another form). Setup+hold depend
on the cell's ability to treat the clock signal (input buffer,
composed of two inverters and wire delays for transmitting the clock
through the whole cell (often not using metal...)).

I am pretty sure better cells exist in industrial libraries,
so i wouldn't bet on perfectness.

correct me if i'm wrong or if what they told me in the university
is crap (both options have equal probabilities).

> Latches have one big disadvantage: they can become transparent.
and sometimes, they do it :-)

This is both an advantage and a drawback so you have to choose
where to use them. For example, the register set uses latches,
both for the registers and their "showdow flags" because we want
to know the flag's value, EVEN during a cycle when it is being
written to...

> In a
> pipeline, you don't want that (unless you're willing to work with two
> or more different clocks). But they are useful for large memories (e.g.
> the caches) where FFs would be too large. The register set may be either
> one; personally, I vote for FFs. IMHO there should be no latches at all
> in the core (caches excluded) -- otherwise, it would be a complete mess.
the mess comes in when we want to make a portable design
(VHDL accept almost anything). I still have no answer to my problem, btw.

in another mail Bruno spoke about a 16*64 cell that can work at 2.2ns,
this puts the maximum operating frequency (.18u) at around 300 or 400MHz.

read you soon and meet nicO at FOSDEM,

>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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