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Re: Rep:Re: Re: [f-cpu] No latches, please !



Michael Riepe wrote:

> Horror! As long as the latch is transparent, you can't be sure that
> its outputs are correct (and stable), so using them is absolutely
> pointless. If you need the value of the flag before the register is
> written, grab it at the input.

I say massive pipelining is useless and multi-instruction processing at
a time really are not the way to design general purpose systems. I see a
CPU as a computing engine... In a Car it is not how many RPM the engine
runs at but the Torque on the rear wheels that move the Car. You have a
transmission to provide for things like hills or starting off. In a
computer to process data you need 4 things 1) where to get the
information 2) what to do with the information 3) the information itself
4) what to do with the information
when you are done with it. Like a 4 stroke engine this is the basic
computing cycle.If you want a faster machine like a 2 stroke engine you
have speed but you burn oil or lose torque or something in the process.
The slowest item memory is really what gives the speed so how to use
memory efficiently is the problem not how many mips you have. To me a
RISC machine still looks like a old computer with a single accumulator
and paged memory and indirect addressing, because of the way it is used.
While things are faster are they more efficient? I read some where a
version of the Pentuim had 4 adders but decoding only could generate
instructions to the pipeline for 3 adders. One never got used. My
grumbles and gripes for today.
-- 
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
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