Rep:Re: Rep:Re: Re: [f-cpu] No latches, please !

[<nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: Yann Guidon <whygee@f-cpu.org>
A: f-cpu@seul.org
Date: 18/02/02
Objet: Re: Rep:Re: Re: [f-cpu] No latches, please !

hi,

nicO wrote:
> Yann Guidon a écrit :
> > nicO wrote:
> > > Some example :
> > > http://www.cse.psu.edu/~cg577/hw1s98.html
> >
> > i have looked and i was surprised by the first
drawing
> > (first attachment) : there is no feedback loop
that memorizes
> > the data :-/ is it precharged logic ? :-(
> 
> Of course not !
> 
> You just discover the difference between a flipflop
and rs bascule.

????????????????????????

both flip flop and latches (modified R/S) have a
storage element,
usually in the form of at least two inverting cells
that are 
tied together. A set-reset is just a form of a
modified
dual-inverter memory loop, where it is possible to
change the state
of the memorised bit (without using driver strength
tricks).
A "transparent latch" is a modified RS with some
control logic.
A FF is a set of 2 chained Transparent Latches with
opposite
clock sensitivity.

unless people lied to me "à l'insu de mon plein gré"
?


>>>> BIP ! Nop ! That's the common mistake. An rs
bascule is composed by 2 latches with the second used
inversed clock. A fliflop use a pulse generator to
trigger a single latch (so it's transparent only few
times, that's create the setup and hold time, that's
why IBM prohibite flipflop).
Beside this 2 idea you could change a little bit by
adding storage element as SRAM cell (wich could be
used instead of the loop).
nicO

Now, if the latching cell has no "feedback loop", and
it is not
precharged, i wonder how it can memorize any data...
maybe using
the gate's capacitance ?

> nicO
WHYGEE
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