[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[f-cpu] virtually or physically-addressed cache ?



Virtual or physical addressing ?
-------------------------------------------
(1) virtually-addressed caches (virtual tags)

+ do address translation only on a cache miss
+ faster for hits because no address translation
- cache flushing on a context switch (example : local data segments will get
an erronous hit for virtual addresses already cached after changing virtual
address space, if no cache flushing).
- synonym problem (several different virtual addresses cannot span the same
physical addresses without being dupplicated in cache).

(2) physically-addressed caches (physical tags)

- do virtual-to-physical address translation on every access
- increase in hit time because must translate the virtual address before
access the cache
+ no cache flushing on a context switch
+ no synonym problem (several different virtual addresses can span the same
physical addresses : a much better hit ratio between processes)

(3) virtually-addressed caches (physical tags)

+ address translation in parallel with cache access
+ same fast hit time as a virtual cache : increase in hit time can be
avoided because address translation is done in parallel with the cache
access
- restrict cache size so that cache index bits shall be in the page offset
(page offset bits are the same for virtual & physical addresses)
- compare the physical tag from the cache to the physical address (page
frame #) from the TLB
- If the cache is too small, only can increase cache size, but still use
page offset bits for the index, by increasing associativity
+ no cache flushing on a context switch
+ no synonym problem (several different virtual addresses can span the same
physical addresses : a much better hit ratio between processes)

Conclusion - which one is better ?
----------------------------------------------
Well, for a FCPU-based machine where there are plenty of processes using a
lot of copy-on-write data segment (same virtual addresses but
maybe-different physically addresses) and dynamic library code segment (same
physically addresses, different virtually addresses), (2)-type and (3)-type
caches would have globally a better hit ratio than (1)-type cache.

(2)-type cache is simpler than (3)-type cache but the latter offers the best
we can find in (1)-type and (2)-type caches.

/christophe


*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/