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Re: [f-cpu] VHDL and delay estimation




Michael Riepe a écrit :


I don't think so. Actually, if you calculate `ss' like this, it won't fit even without the half adder. But I don't know what's around the circuit. Maybe there is room somewhere else.

just to know the cost of a xor (in fact the half adder): 2 gates deep?

--

~~ Gaetan ~~
http://www.xeberon.net


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