# Re: [f-cpu] SIMD and exception

hello
I got some interesting answers about exception, and what about SIMD (this is blocking me for the moment)

gaetan@xeberon.net a écrit :

Hello F-World

Two other questions today :)
1) i'm thinking my current way to handle SIMD will not be correct. For the moment, in each stage, i check if i do operations in 32 bit or in 64bit. The problem is it's add a MUXto each stage... and it's at lease 2 gate deep.
In fact i do in each stage:
if (OpSize = single) then
make operation op1 with operands as single float
else -- opsize = double
make operation op1' with operands as double
end if;
and the comparison are with 2 bit vector (00=32bit, 01=double), so it's huge for each stage...

So i think to other methods:
- select in the good way in the first stage (with a decoder, to prevent unused path to switch transistors), and select the good result in the last stage. The problem is it will use twice more component (for instance i use only one 64 bit generic_adder for both SIMD format, but now i will to do addition for single and an other addition for double float). It will also add twice more registers. The problem here is the area.
- to convert everything in 64 bit and do all operation in 64 bit (i think this is how the pentium works), BUT the problem is in the last stage, i will have to cut the mantissa and exponent, and this will add some logic, so increase the number of stage by at lease one (especialy for the rounding step)
For the moment, i think everything should fit into 4 cycle, but some problem can occurs, so it may use 5 cycles at the end.
So i would like to know what do you think about that.

And an other thing i don't understand;
I was told that
if ( thing = '1') then
A := not B;
end if;
has 2 gates of delay (d=2)

And according to Yann a MUX2 is d=2

But after, Michael told me the shifter only is d=LN (for each bit of N vector (LN bit long) there is a MUX)... so it should normaly takes d=2.LN...
so here is my problem... :(

And is it the same way for logic equation:
i mean (A, B, C are std_ulogic, not vector):
(A and B) or C
d=2 ?

(A xor B) xor C
d=2?

u = (Sa and not(s) ) or (not(de xor Sa) and s)
is d=3?

thanks thanks thanks thanks

--

~~ Gaetan ~~
http://www.xeberon.net

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