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Re: [f-cpu] "A structured VHDL design method"



On Mon, Feb 23, 2004 at 05:08:16PM +0100, nico@seul.org wrote:
[...]
> The main practice is to use records and 2 processes by entites (one
> combinational and one synchronous). The goal is maintenability. A must
> read !

Do you really think it's a good idea to put the "stuff" from 5 or 6
uge pipeline stages into a single process?  I don't.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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