Re: [f-cpu] "Tree"

[Kim Enkovaara <embo@mpoli.fi>]

> > I have just read the package from Whygee and i have found an horror :
> > specific entities for trees.
> a binary balanced tree for buffering signals, yes.

You should never do buffering at RTL stage. Let synthesizer do it, and if
really necessary do it manually for the few places that need it during
synthesis. Manual tree building consumes quite much simulation resources
and slows down synthesis. I think DC can rip out the buffers and rebuild
the tree fortunately, but it needs more time for that.

> 1) never trust a compiler/synthesiser, unles you can look at the output

Usually synthesizers do much better job at tree building than the designer
(and usually in many other places also). In physical synthesis the
syntheziser even places the buffers and balances the delay in whole tree.
I doubt you plan to manually place all the buffers to balance the trees.
Some branches might need more than one buffer to create extra delay to
keep skew low etc.

In the beginning of 90s the synthesizers were so buggy that you needed
always manual checking, but nowadays they are very good.

> 3) Synopsys is not the only compiler on earth. We try to be as open
> as possible to other EDA toolchains which may not contain smart
> optimisations. If we design code only for Synopsys then it could be
> useless with other tools. On top of that, it is not even monetarily
> free... which explains why few people have ever accessed it.

Synopsys is almost the only Synthesizer for ASIC. There is Synplify ASIC,
but it can do even higher level optimization than Synopsys DC. 

> 4) if the compiler is smart enough to understand what the fanout
> tree does, then it is able to do a better work. Otherwise, we have
> a minimal failsafe. I am thinking of the "extreme case" if we have
> to use Alliance as a last resort...

Problem is that this makes synthesis times longer in many cases.

> 5) Evaluating the fanout's "cost" is necessary, otherwise our
> "time budget" will not hold. When writing in RTL/HDL,
> one does not necessarily "see" that an operation requires a large
> fanout and this counts in the design budget. A "hidden" fanout

I think during HDL coding the coder should check the synthesis results and
identify places with huge fanout. But not balance the signal trees.


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