Re: [f-cpu] "Tree"

[Juergen Goeritz <goeritz@oekomm.de>]

On Thu, 10 Jan 2002, Kim Enkovaara wrote:
> I think same applies to state machines. I consider state machines done
> even with RTL level. And if the SM is done in RTL I think the
> synthesizer should select the coding of the state vectors etc. Usually it
> has better knowledge about the constraits of the architecture and what
> creates fastest solution. Optimal solution I think is higher level SM
> description where you only draw states and tell state transition rules

Igitt! My experience is that drawings should only be an output
but not an input to the design. Otherwise it's real SM and it
costs you nerves without end to include those changes into the
design. 

> etc. The problem is how to rely that high level description directly to
> synthesis level. Usually that high level SM is converted to RTL code,
> after that the synthesizer reads the RTL code and sees that it is a SM, 
> and optimizes it at high level again.

Why convert to RTL code. Every synchronous statemachine can
directly be translated into a function table without thinking.

The only statemachines I have great respect of are those
that treat each input signal as a clock and remember the
contence by the device delay feedback only (no registers).

JG

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