Re: Tr:Rep:Re: [f-cpu] "Tree"

[nicO <nicolas.boulay@ifrance.com>]

Ben Franchuk a écrit :
> 
> nicolas.boulay@ifrance.com wrote:
> 
> > >>>>>>Maybe you should read about F21. It's a
> > complete assynchonous design. It run at 2 ns for a
> > cycle for a 0.8um technology. It doesn't use neither
> > double rail logic nor hand checking. I was in contact
> > with one of the guy from  the team who write it. But
> > i don't know how they time there cpu.
> > nicO
> 
> Hmm A Forth machine pops back up again?
> .8um how fast is that? How many real gates in the pipeline.
> This includes the gates in the pipeline flipflops.
> How is the logic partitioned. What is the architecture?
> What is the latency? In 2 ns what the % of gate delay time,
> transmission time % and fixed overhead like clock skew %?
> What logic is used - bipolar, nmos , cmos , ecl , tube?
> Yes tubes could make a comeback for tiny structures.

it was 0.8 um CMOS process. There is no flipflop nether pipeline : it's
fully asynchronous ! To be more precise the adder take 4 "slot" time.
That's why i give the period time and not the frequency : because there
is no clock !

> 
> --
> Ben Franchuk - Dawn * 12/24 bit cpu *
> www.jetnet.ab.ca/users/bfranchuk/index.html
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