Re: [f-cpu] latest gcc & immediate addressing [Was: BOUNCE f-cpu@seul.org:...](fwd)

[Yann Guidon <whygee@f-cpu.org>]

wouah there, there seems to be some confusion ....

cedric wrote:

> > Unfortunately, this is not always true: the ROP2 (logical) operations
> > behave differently. They really suck when it comes to efficient non-SIMD
> > code generation (in particular, conditional branches); we should talk
> > about changing the ISA definition (without sacrificing the current
> > functionality, of course). E.g. we could define the following variants:
> >
> >    // these are new
> >    <op>.<and|or>.<size>    // truncates result to chunk size
> >    <op>.<size>             // truncates result to chunk size
> >    mux.<size>              // truncates result to chunk size
> >
> >    // these correspond to the current ones without `s' prefix
> >    s<op>.<and|or>.<size>   // always operates on full register (size used
> > for combine)
> >    s<op>.<size>            // always operates on full register (size is
> > ignored)
> >    smux.<size>             // always operates on full register (size is
> > ignored)
> >
> > Then your assumption would be valid again.
> >    
As far as i remember, the ROP2 instructions follow the general rule :
the "size" field indicates the number of bits to write back.
That is : one can do a OR on one byte or word, and the rest will
be cleared.

Then comes the problem of the chunk size of the COMBINE mode,
it requires 2 more bits which are taken from the IMM mode
so only the register form is possible when combine is needed (IIRC).

> > > >    - logic operations take 9-bit signed immediate operands.
> > > >        
> > > uhh .. my 2.7 manual doesn't state it :( Where can I find it ?
> > >      
> > Dunno. I read it somewhere (maybe in the source code), and implemented
> > it in both the assembler and the emulator.
> >    
> Hum, I have a problem here, I don't find any empty room for that in our ISA. 
> How did you implement it, by using some of the OP_CODE bits ?
>  
IIRC, i have "stolen" a few bits from the flags.

To sum up, a "normal" ROP2 has
8 bits of opcode
2 bits of size

6 src1 or 9 imm9
6 src2
6 dest

and i forget the mode bits.

<clic clic clic>

ok i found in the file FORMAT.txt :

ROP2 :
27-31 : Opcode
24-26 : function
22-23 : size flags (normal ones)
20-21 : Combine size flags (not used yet, only 00 is used for bytes)
18-19 : mode (0=normal, 1=mux, 2=Combine AND, 3=Combine OR, but see the 
tables
   for a more up to date definition)
12-17 : Reg 0 / src1
6 -11 : Reg 1 / src2
0 - 5 : Reg 2 / dest / src3 for mux


ROP2i :

27-31 : Opcode
24-26 : function
22-23 : size flags (normal ones)
21 : SIMD flag [set if the imm8 is duplicated in all chunks, otherwise 
it is sign-extended]
20 : sign extension bit for imm8
12-18 : imm8
6 -11 : Reg 1 / src2
0 - 5 : Reg 2 / dest / src3 for mux


Does this solve the problem and answers the questions ?

> Cedric
YG

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