Rep:Re: [f-cpu] statistics of direct indexing usage

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: devik <devik@cdi.cz>
A: <f-cpu@seul.org>
Date: 08/01/03
Objet: Re: [f-cpu] statistics of direct indexing usage

> > Simple L/S: 2236, post-update L/S: 558, imm-offsets: 2594
> >
>
> The question was more the comparaison with the 8 bits imm operand.
> Because 8 bits use 2 flags bits, not all reg-reg operations could be
> handle using 8 bits imm. So the question was what is the occurence of
> this impossible 8 bits immediat instructions, and is it harmfull for
> speed ?

well the test I have done just now was targeted to addressing
mode with direct offsets.
But to reply your question I did quick change of allowed constants
from 8 to 6 bit in all immediate representations.

8bit imms:
total insns: 27509
Arithm/cmp with immediate: 2212
6bit imms:
total insns: 28157
Arithm/cmp with immediate: 1588

so that by shortening imm bits by 25%, we also can use
them in about 25% less occurences. It seems that probability
density is constant for imm occurence in the code.
While we have 624 less immediate ops, total insn count is
higher by 648 - it is loadcons for each such op - it doesn't
mean that the code will be really slower because loadcons might
fit into otherwise unused schedule slot.
We need to finish gcc to produce correct code for MR's AS and
then create simulator - then we will see.

Is it what you wanted to know ?

>>><mode=chieur>
Not really. :) It's an interresting number however. The idea was better
to add the 6 bits immediat adressing mode rather than _replace_ the 8
bits mode. 

By using 8 bits immediat, you can't use some flags combinaison. So what
is the impact in the generated code (how many instruction would like to
use this particular combinaison?).
nicO
</mode=chieur>

devik

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