Re: [f-cpu] x86-64 long article

[Yann Guidon <whygee@f-cpu.org>]

hi,

nico@seul.org wrote:

> Yann Guidon <whygee@f-cpu.org> a écrit :
>
> > hi !
> >
> > (maybe we can go to the francomoule's tribune ?)
> >    
It didn't seem to work anyway ...

> > Michael Riepe wrote:
> >
> > > On Fri, Jan 24, 2003 at 01:01:27AM +0100, Yann Guidon wrote:
> > > [...]
> > >
> > > > > Sounds like the return of the G-chip...
> > > > was it ever away ?   
> > > Haven't heard from it for a long time...
> > >      
> > i don't like to speak about things that drive people crazy :-)
> :) If you want more than 8 fcpu in a single machine use multicore chip ! :)
>  
and if we want more than 8 chips ?

If the introduction frequency is around the realistic (but not easy anyway)
frequency of 200MHz, then at that time 3.2 GHz CPUs will be common place
and you will need 16 CPU to catch up in MHz rating.

> > > > Or somebody found the way to multiply the number of pins
> > > > without exploding the F-Chip's cost ?...
> > > I still prefer high-speed serial links.
> > we can't access this technology, or the die's price climbs.
> ???? N'importe quoi ! (Irgenwas ?)
>
> The lvds link run ar 600 Mhz/pin. 1Ghz will be soon reach. 10 Ghz is plan.
Like F-CPU.
But F-CPU should be able to run on 'old' technologies.
Do you believe that 10Ghz links will be possible using .35u ?

> We can use this for connecting F-cpu like Athlon 64 does (no big and fat routing chip that cost a lot and add latency like a northbridge in PC chipset).
>  
hmmm LVDS needs 2 pins, so it's the same bandwidth as 2 pins at 300MHz.

Plus, if you use serial encoding, there is more latency for a single packet.

> But technology like hypertransport could be cheaper because you could reuse a lot of test material and module done for it. "Standard" is always cheaper.
>  
oh yes, AMD will allow us to use their test equipments ....


> > > Something that's compatible
> > > with one of the existing serial "buses" would be even better. But...
> > yep, you named it.
> > eing compatible with Intel and other has some risks ....
> The foundry will have to pay the licence but it could be cheaper that create all new design for such bus.
>  
AMD and Intel are slowly switching to .13u,
this is not possible to use it unless you make millions of chips.

"old fabs" or production lines using .35u is more realistic
because their masks are not as expensive and the lines' costs
have been amortized.

> > > > > Too bad that 8b/10b encoding and other good stuff are patented.
> > > > Well, i have thought for a long time about an oversampled synchronous 
> > > > communication path.
> > > > But the maths behind it are too tough for me :-(
> > > >        
> > > Hmm... what exactly do you have in mind? Dump your brain to my
> > > standard input, please :)
> > But not in public.
> > It's an old idea (3 or 4 years ?)
> > but i want to be the first to find the solution ;-)
> You want to create digital modulation put in a wire ?
???


> LVDS + data driven transfert (the clock came from  the sender
>
> and not from a global clock so you could manage the jitter)
isn't this also called "source clocking" or something like that ?

> do a pretty well job at 1 Ghz ! And it don't need
>
> modulation/demodulation module to be used.
>  
One prolem i have found with current technology is the
"negociation" of the frequency between two different devices.
Source clocking is one of the answers but it's not enough.


> nicO
>  
YG

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