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Re: Rep:Re: [f-cpu] I forgot to tell you...



hi !

Michael Riepe wrote:
> On Thu, Jul 04, 2002 at 08:25:45AM +0000, Nicolas Boulay wrote:
> [...]
> > - i started popcount and mostly finished the register set.
> Ah... I wundered why they were marked green in the latest picture.
:-) Kein Wunder hier...

> > - still "in the pipeline" : finish popcount (btw Michael's help
> >   is welcome because i don't know how to you his generic adders),
> >   rewrite (mostly) INC, and start BIST.
> What do you want to add? How big are the operands?
For the popcount, i have to solve the 4-bit input -> 3 bits ouptut
logic operation (bit 0 is a AND-reduce and bit 2 is XOR-reduce
but bit 1 is not straight-forward at all). Currently i do it with a
lookup table in the integer world (that's lame but it should simulate
fast ;-D). Then there is a row of 8*(3+3=4) adders to make the byte results,
4*(4+4=5) adders for the 4 shortint results, 2*(5+5=6) for the two lontgint
results and a final 6+6=7 adder for the full 64-bit result.
Currently, i do this with the lame (from memory)
  subtype type_result6 is integer range 0 to 32;
  type array_6 is array (1 downto 0) of type_result6;
  signal tmp_6 : array_6;
approach with some loops in which i simple perform the addition as is.

so what i need is entities that perform 3+3, 4+4, 5+5, 6+6 and 7+7,
that's that simple :-) and the boolean equation of bit 1 of the 4->3 bit
reduction woud be handy, too.

> > Btw, for those who still want a C emulator : i care even less,
> > now that i have found that ncsim runs 60 times faster than simili*
> >
> > >>> Ouch ! 60 x ! 2 or 3 could be acceptable but not 60 x ...
> > nicO
remark : that was a measurement i made on my laptop (everybody knows
how it sucks), the difference my change with other configurations.
And it was for running Michael's exhaustive loops. I don't know how
it will behave with a full CPU : cache locality will not work and
the speedup might drop a bit... i have only 128KB of L2 on my Celeron
and a good big XEON or ATHLON might help accelerate that too :-)

> > and 120x faster than vanilla. Riviera is almost (some %) as fast
> > as ncsim. So the "easy" solution is to get a free Riviera license :-)
> Did they offer us a full license, or only the 20-day trial license on
> the web?
when you get the distro, there is a 20-day "restricted" evaluation period.
It is then unlocked on a request to ALDEC, which seems to be very liberal
with their 3 months "unlimited" evaluation period (all limits are gone,
except the time, but like Simili, it seems to be updated regularly on their
site and it might be a way to force the upgrade). I have no answer to the
question "and after 3 months ?". Cadence automatically sends me a new
license some days before mine expires, but the ALDEC policy is not totally
clear concerning F-CPU. But it might be worth it to try the 3-months thing,
just for the test run. It's a 37MB download, but it contains Verilog and EDIF
simulation, code coverage, random init, GUI, TCL, etc... it's a kind of
"advanced" Simili but Simili still wins concerning the installation speed
and ease. I've found that not only Riviera conflicts (on paper) with Modelsim's
tool names (that's solved through the use of direct paths), but also with
Vanilla (that's solved with an option that changes the current library directory).

I'll update the VHDL_HOWTO whenever i find time...

nicO :
> Is it possible to have 2 or 3 vhdl files to test the speed of vsim at work ?
i measured the times to run iadtest5 and iadtest6.vhdl, as found in Michael's
snapshot. i'll upload mine ASAP so you have the latest scripts.


>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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