Re: Rep:Re: [f-cpu] I forgot to tell you...

[Michael Riepe <michael@stud.uni-hannover.de>]

On Fri, Jul 05, 2002 at 03:37:07AM +0200, Yann Guidon wrote:
[...]
> > You can use my CIAdd procedure from the Generic_Adder package. Here's
> > how to use it:
> > 
> >         function "+" (A, B : in std_ulogic_vector) return std_ulogic_vector is
> >                 use work.Generic_Adder.CIAdd;
> >                 constant w : natural := A'length;
> >                 alias aa : std_ulogic_vector(w-1 downto 0) is A;
> >                 alias bb : std_ulogic_vector(w-1 downto 0) is B;
> >                 variable yy, cc : std_ulogic_vector(w-1 downto 0);
> >                 variable pp, gg : std_ulogic;
> >         begin
> >                 CIAdd(aa, bb, yy, cc, gg, pp);
> >                 -- we only care about yy here
> >                 return yy;
> >         end "+";
> 
> you mean, i copy it verbatim in the code ?

This function, yes. You can of course call it differently (redefined
operators are tricky sometimes).

I probably should add something like that to package Generic_Adder.

> > That should work at all operand sizes you need. But note that the
> > delay will probably be big (d=4...5 per CIAdd), that is, a 64-bit
> > result will need 4 pipeline stages :( We may reduce that to 3 if the
> > adders are broken down into their components (CIA_Row and CIA_Inc).
> i don't understand well... here the operands are 3 to 6 bit wide.

The function above can add two operands that have the same size.
Whether they both have 3, 4, 5, 6 or 64 (or 640) bits doesn't matter.

The delay of the outputs, however, depends on the operand size: for
1...4 bit operands, the delay is d=4; for 5...8 bit, the delay increases
to d=5.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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