Re: [f-cpu] Remarks to most recent (2002/07/04) snapshot

[Yann Guidon <whygee@f-cpu.org>]

hi again,

Michael Riepe wrote:
> EU_IDU (not ready yet):
>         The 8-bit subtractor can be replaced with misc.Generic_Adder.CIAdd.
i'll try to do it.
Cédric is busy with other things, but i'll do it anyway.

> EU_INC:
> 
>         The `bloc_and' entity and the tree of AND gates can probably
>         be replaced with my misc.Bit_Manipulation.cascade_and function.
>         Only the SIMD stuff needs to be added.
> 
>         Since only INC/DEC/LSB is supported, will there be a complementary
>         unit for CMP/MSB?
i don't think so, at least yet. INC now is a 1-cycle unit,
i wanted to add a priority encoder but popcount does it nicely.
i also wanted min/max but it can be done with a substract with saturation
followed by a MUX in ROP2.

> EU_POPC:
>         Currently uses function "+" from IEEE.Numeric_Std (but that's
>         going to change, fortunately).
sure :-)

>         Please do NEVER use IEEE.Numeric_Std in your designs
>         (it is acceptable in testbenches, however).
that was only a first version that could do the job in simulation.

> I'm also missing delay indications in the new EUs. Do they all satisfy
> the 6G/10T rule? I doubt that e.g. the 8-bit divider from EU_IDU fits
> into a single pipeline stage, no matter how fast the subtractor is.
that's a specific IDIV problem...

Concerning the others, they are indicated in CAPABILITIES.txt.
it's not always up to date but it gives a rough estimation.
POPCOUNT will be updated too.

> Concerning component instantiations:
> 
>         The VHDL'93 `label : entity blah' instantiation style may be
>         more convenient, but it requires blah to be analyzed first.
>         With '87 style, you can analyze the source files in any order.
>         And it will work with ALL tools (one never knows...).
> 
> (Yann, you can put this into the VHDL HOWTO).
i'll do

> In order to speed up simulation and synthesis, it's also a good idea to
> avoid signal assignments whenever possible. Use processes and sequential
> statements, and put temporary values into variables, not signals. Signal
> assignments are only needed for inter-process communication, pipeline
> registers and the like.
ok.

>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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