[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[f-cpu] little feed-back from the libre softawre meeting
- To: <f-cpu@seul.org>
- Subject: [f-cpu] little feed-back from the libre softawre meeting
- From: "Nicolas Boulay" <nicolas.boulay@ifrance.com>
- Date: Fri, 12 Jul 2002 19:23:02 GMT
- Delivered-To: archiver@seul.org
- Delivered-To: f-cpu-outgoing@seul.org
- Delivered-To: f-cpu@seul.org
- Delivery-Date: Fri, 12 Jul 2002 15:23:19 -0400
- Reply-To: f-cpu@seul.org
- Send-By: 147.210.68.141 with Mozilla/5.0 (X11; U; Linux i686; en-US; rv:0.9.9) Gecko/20020412 Debian/0.9.9-6
- Sender: owner-f-cpu@seul.org
Cedric, Whygee and i have travel to Bordeaux to assist to the libre
software meeting ( lsm.abul.org ). Lots of people from very differents
open/libre source word are comming.
It end tomorow. The following is a little feed-back from our discussion
with different people. (we don't know where is whygee so i send you
without his rereading)
---
Security point of view
We have seen Frederic, pappy Raynal (main writter in MISC, french
securities newspaper) and Bradley Spencer who write the grsecurity
patch.
They propose :
read, write, exec bit + at least 3 rings (super user + user +
something like for library,...)
From Cedric thinks :
we need 3 sr : to set or unset the tbl
something to change the ring
for vm writter we must enable or not the read
access to sr(trap on read AND write)
From discussion with a Hurd guy (Neal Wafield)
16 kb for a page is a little bit to much
8 kb could be enough
all new processor have between 5 to 11 page size !
alpha handle an 8 bits fields for virtual area number (for tlb and
caches) -> sw must avoid collusion.
we should try to implement L4 (hurd main kernel) to verify the
process management of the f-cpu
From my view,
none polling thread barrer should be implemented (for tigh
multithreaded application on multicpu)
Conclusion :
implemented L4
change specification of the tlb (no more the kind of caches use
but an 8 bits fields)
Looking for technics to handle different page size on the same
memory for (tlb) to avoid the use of many independant memories
Hope this help. Comments ?
nicO and Cedric
______________________________________________________________________________
ifrance.com, l'email gratuit le plus complet de l'Internet !
vos emails depuis un navigateur, en POP3, sur Minitel, sur le WAP...
http://www.ifrance.com/_reloc/email.emailif
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu in the body. http://f-cpu.seul.org/