Re: [f-cpu] little feed-back from the libre softawre meeting

[Cedric BAIL <cedric.bail@free.fr>]

En réponse à Christophe Avoinne <christophe.avoinne@laposte.net>:

> I'm discouraged... your diagram about F-CPU is speaking about ICACHE
> and DCACHE, am I wrong ?

No.
 
> They are separate !!!! I'm explaining why it is a nonsense to speak
> about 'r','w' for code page and 'x' for data page, especially if you need a
> seperate TLB for ICACHE and DCACHE. Of course, if you used a unified TLB
> for ICACHE and DCACHE, well we can can have entries with 'r', 'w', 'x'.
> 'r','w' would be relevant accessing DCACHE and 'x' for accessing ICACHE.

I now understand you, I was thinking about an unified TLB for ICACHE and 
DCACHE. But it can be a question. Personnally, I think that they must unified,
so that the software can allocate the good ratio of entry for code and for
data.

> > > Seriously,
> >
> > > 'x' : executable -> ICACHE, because it is the instruction fetcher
> > > which needs to access bytes in code page : IT NEVER WRITES !!! so 'x' is
> > > in fact a disguised 'r' and 'w' a non-sense.

> > If I understand what you say, we can't write "automodify" code.

> Oh my god !!!!! i turn into french explanation :
 
<snip french>
I think I know I understand your question, it isn't about the rwx bits, but
more on the unified TLB for data and code, now I am right ?

> > > 'r','w' : readable, writable -> DCACHE, because it is the LSU which
> > > needs to access bytes in data page : IT NEVER EXECUTES !!!

> > Why not, we must not block this possibility.
 
<snip french>

Currently the TLB is placed before any access to memory. You can't acces any
cache without asking the TLB. (I am not sure about the cache in LSU and 
fetcher).
From what Yann say, I understand that we have only one unified TLB.

Cedric
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