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Re: [f-cpu] TLB design




> > Oh well i supose we can have a saturate counter ? no, i'm joking :)
>
> A single `used' bit *is* a saturated counter (counts up to 1).
>
> > Usually a SW TLB raises an exception when a miss cache occurs, so we can
> > timestamped the page discarded (linux for example have a info block per
> > physical page) and use it when a slow timer is walking the info blocks
to
> > lookup for a ideal candidate (timestamp least recent I think). I suppose
of
> > course that there is much more physical pages than entries in TLB.
>
> Cache miss? You mean TLB miss, don't you?
>

Yes, sorry I sometimes tend to consider TLB as a special cache (the only
difference is the hold data is not the content of memory but a physical
address instead, but TLB works like a cache indeed).

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