Re: [f-cpu] Free synthesis tool for Verilog and other links

[Just an Illusion <illusion_to_net@yahoo.fr>]

Hi,

I have yet tested this tools (on this version, if well remember), but it 
seems have too many limitations on supported verilog subset.

It's why we have decided (in my company) to do not use it.

For information the Alliance project from the lip6 laboratory (from 
university of Jussieu in France) have a free synthesize tool with a 
capability of vhdl keeping. But the rtl vhdl subset is too limited to 
support a "real" industrial model.

http://www-asim.lip6.fr/alliance/

If we want use this type of tools (on the project), we need well 
identified the input restrictions on the language, and code with it.

Cheers,
Just an Illusion

Michael Opdenacker wrote:

>Hello,
>
>As I told some of you last week in the LSM event, a free synthesis tool
>exists for Verilog (unfortunately not for VHDL):
>
>http://icarus.com/eda/verilog/
>
>Here is also a nice page full of useful links, for those who may not
>know it:
>
>http://www.eedesign.com/resources/opensourcelinks.html
>
>Good luck for your great project!
>
>	@:-)
>
>	Cheers,
>
>	Michael.
>

-- 
______________________________
"The matrix is my world, I am a shadow.
Shadow in world, shadow in life. Don't try to keep me,
I am a Corpo's Killer.
Don't follow me or die..."
		The KingWalker - 1996



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