Re: [f-cpu] Free synthesis tool for Verilog and other links

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Yann Guidon wrote:
> alright, but it's like C : we have to use them anyway :-/
But what else is open source that not written in C?

> First thing first : we have to define what it does, before defining how.
> Later "architectures" of each entity can be further optimised, but a simple
> behavioural code is first necessary...

  That is true. I was just reading on the web that the biggest problem
with software is keeping the comments up to date. Do you have a
procedure for that?

> i don't understand the last part of the question.
> However, VHDL allows you to replace one version of a module ("entity" in
> VHDL jargon) with another version ("architecture" in VHDL, which can be
> written differently or even include a technology-specific description
> (hierarchical or flat netlist for example).

   I can do that with schematics too. I will re-state the question.
Is the net-list in a form that can still be read by people if you want
to tweek the code by hand?

-- 
Ben Franchuk - Dawn * 12/24 bit cpu *


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