Re: [f-cpu] Free synthesis tool for Verilog and other links

[nico <nicolas.boulay@ifrance.com>]

Michael Riepe a écrit :
> 
> On Thu, Jul 18, 2002 at 06:34:48PM +0200, Yann Guidon wrote:
> [...]
> > However, VHDL allows you to replace one version of a module ("entity" in
> > VHDL jargon) with another version ("architecture" in VHDL, which can be
> > written differently or even include a technology-specific description
> > (hierarchical or flat netlist for example).
> 
> The question is whether such an architecture can still be considered
> `edible source code' or whether it is `binary'. Imagine someone who
> takes the original source, creates an optimized netlist from it and then
> edits it... that's almost like bit-twiddling in .o files.
> 

It's clearly not a problem. GPL apply for every thing that have a
prefered forme for modification (source code in C, vhdl, but i have seen
that a simple picture could be GPL, the prefered forme of modification
is the picture it-self)

I think we must defined how a entity could be replace by a technological
one (imagine replacing the register bank by a specific design,
technology dependant) : it's good for speed. But if we allow to much
"closed" change, somebody could change what ever entity he want, without
releasing it in "libre" licence. Maybe could we tolerate an exchange if
the new code have exactly the same beavioral of the previous code. But
if there is some architectural improvement, this could be hidden too...

That's seems endless... :-/

nicO

> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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