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Re: [f-cpu] Free synthesis tool for Verilog and other links



> I think we must defined how a entity could be replace by a technological
> one (imagine replacing the register bank by a specific design,
> technology dependant) : it's good for speed. But if we allow to much
> "closed" change, somebody could change what ever entity he want, without
> releasing it in "libre" licence. Maybe could we tolerate an exchange if

How about marking all the blocks where this kind of technology dependent
optimization can be done. For example in register bank the optimal
solution can be some block from the vendor libraries that is proprietary
and NDA covered. And the entity encapsulating those "commercial" blocks
could also contain some glue logic to adapt the interfaces.

For the control logic this kind of technology dependent twiddling should
not be so important. Or if it is needed they should be functionally
identical.

=============================================================================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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