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Re: [f-cpu] Conditionnal Load and Store


Cedric BAIL wrote:
> Why didn't we have conditionnal load and store. I mean somtehing like storez,
> storenz, loadz, loadnz, ... It can be really usefull and we can do with that
> all what we can do with predicate I think.

conditional loads/stores are a corollary of the conditional moves.

IIRC it appeared that these instructions were in fact needed,
when we were discussing about the semaphores done with LL/SC.
"Store conditional" is this thing.

By the way : condition 3 is still reserved for FP, but we could
simply connect it to the LSU : LL/SC would then not need any specific
opcode. it sounds easy and logical, what do others think ?

> It will really help the compiler I think to produce efficient code without
> stupid jump, but it will cost 8 OP codes for load and 8 more OP codes for store.
that's not a real problem. it is important to keep the instruction
orthogonal, and we have enough room, particularly if you consider that
Loads and Stores make 30 or 40% of a program.

Could you add a page about conditional loads and stores to the manual ?
(that is marked "highly speculative")

i believe i told this on the list, but no solution is known yet.

Currently, the "MSB" condition just takes the 63th bit of the
pointed register. But what about larger registers ? what about
small integers ?

I stick to the original definition because i don't have a satisfying
answer to both questions.
 - larger registers is not really a problem because a task or
   system will always start up in "compatibility" 64-bit mode,
   with all 4 size flags set to emulate the "standard" 8-16-32-64 sizes.
 - small integers can't be tested because we don't have enough bits
   to code the size. The corresponding bits are used for other flags.
   Except maybe in the conditional move, but these size flags indicate
   what size to move, not the size to test.

> Cedric
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