We've been talking about this some days ago on the web. It contains the currently missing parts from EU_INC (cmp, min/max/sort, msb0 and msb1) and may be merged with EU_INC one day (that is, both units may share I/O ports). The implementation is rather simple; there's still some unnecessary code duplication, and the layout could be improved as well (e.g. by `interleaving' the trees for different chunk sizes). But it works :) The timing is pretty tight: I had do violate the Six Gate Rule in the second stage (but there are only and/or gates and muxes - I guess it's not a problem). Synthesis reports are welcome, as usual. For the record: all operations have a latency of two clock cycles. It is possible to perform 8-bit compares in a single cycle, but that will require an additional unit which can do nothing else, or a more serious violation of the Six Gate Rule. Sometimes I think we might do better with a `Twelve Gate Rule', half the clock frequency, and shorter pipelines - at least when I look at benchmark results of the Pentium 3 and 4 families... the P4 clocks are much higher, but the CPUs aren't much faster. -- Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de> "All I wanna do is have a little fun before I die"