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Re: [f-cpu] New snapshot for EU_INC and EU_CMP



hi all,

Ben Franchuk wrote:
> Michael Riepe wrote:
> > I doubt that you can get away with 8 cycles. From my experience, 64-bit
> > CMP alone needs 1 level of 2-xor, 3 levels of 4-and, 1 level of 2-xor,
> > 1 level of 2-and plus 3 levels of 4-or, giving a total of 9 levels.
> >
> But would not CMP be better defined like the add operation
> One cycle for small operands
> Two cycles for full compare

i believe (for a few months when the evidences became so obvious)
that this idea creates problems, at least for the "common" operations
(MUL is another case). i think i'll drop the special case of 1-cycle
for 8-bit add/sub (and thus for cmp).

the reason is the Xbar structure which already has too many ports.
Furthermore, the layout could become too complex because units
should try to share input and output ports. Having an output port
in the middle of a unit (ie : ASU) reduces the opportunities to share
that port with another unit.

it's probably not clear yet but the conclusion is that variable
latency is not good for the small units (CMP, ASU, SHL)

WHYGEE
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