[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] New snapshot for EU_INC and EU_CMP



Hello,

I have found some other mistakes (unsupported code for the VHDL RTL 
Synthesis subset).

See the attached example I give in thread : [f-cpu] HDL coding style.
In the message from 07/30/2002 at 02:54 PM

Just an Illusion.

Just an Illusion wrote:

> Hello,
>
> I have read your code and, unfortunately, I have found an 
> unsynthesisable structure :
>
>   tree_find_lsb : entity find_lsb
>                               ^^^^^
> the entity keyword is not supported at this position.
>
> See IEEE P1076.6-2001 for more information on VHDL RTL synthesis subset.
>
> Just an Illusion
>
> PS : If some one need a version of the IEEE P1076.6-2001 standard, I 
> can upload a version on seul.org.
>
> Etienne LABARRE wrote:
>
>> Hi all,
>>
>> New snapshot include a lot of changes and features :
>>
>> INC unit and CMP unit are now two different units, for simplify and
>> decrease latency
>>
>> Both units are based to the same component : find_lsb
>> It's a binary tree for find the first null lsb in a word.
>> It supports SIMD operations (size of chunk = 8, 16, 32, 64, 128, 256
>> bits)
>> It's based to only one function : and_reduce. It's is a standard
>> function of ieee.std_logic_1164 library.
>> Latency of find_lsb is not exactly know, but i can estimate this
>> to 3 level of 4-and, and 1 level of mux, or more exactly 2 level of
>> 8-and, and 1 level of mux. The precise latency is not important,
>> because max latency will be fixed by timing constraints during 
>> synthetisis process.
>> (It's an explain of my choice of standard function. "Just an
>> Illusion"
>> will can explain this more easy that me, i think...)
>>
>> For INC unit, the data flow is :
>> 1 level of mux
>> find_lsb : 3 level of 4-and, 1 level of mux
>> 1 level of xor
>> 2 level of mux
>> total is 8 levels.
>> Critical datapath is only for ABS operation.
>>
>> Supported operations :
>> INC, DEC, NEG, ABS, LSB0, LSB1
>>
>> All operations are tested by my testbenches.
>>
>> For CMP unit, the data flow is :
>> 1 level of xor,
>> 1 level of mux,
>> find_lsb : 3 level of 4-and, 1 level of mux
>> 2 level of mux,
>> total is 8 levels.
>> Critical datapath is for CMP, MIN, MAX, SORT operations.
>>
>> Supported operations :
>> CMP, MIN, MAX, SORT, MSB0, MSB1
>>
>> Today, only CMP, MSB0 and MSB1 are tested by my testbenches. Todo :
>> test for others operations.
>>
>>
>> All operations can need only one cycle, if we accept the 8 level of 
>> gates
>> latency.
>>
>> Etienne.
>>
>

-- 
______________________________
"The matrix is my world, I am a shadow.
Shadow in world, shadow in life. Don't try to keep me,
I am a Corpo's Killer.
Don't follow me or die..."
		The KingWalker - 1996



*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/