[f-cpu] Whats going to happen when the VHDL is done?

["Marco Al" <marco@simplex.nl>]

What about the design of custom cells/manual floorplanning/static&dynamic timing
analysis etc? AFAIK the big boy's dont even use the commonly available stuff for
this, high performance processors are in a class of their own... especially if
you want to compete with something like the P4 (which you do seem to, otherwise
having pipeline stages that shallow makes no sense). If you just want to plonk
VHDL through a synthesizer worrying about 10th's of ns is futile.

I know its a bit counterproductive bringing this up... but somoene has to have
some idea what to do once you get there right? Just curious...

Marco

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