[f-cpu] How to increase the mip/mhz ratio.

[nicO <nico@seul.org>]

After the IEEE conference on today processor, i have understood the udge
total amount of control needed to make superscalar processor. You need
to verify coherency with a scoreboard and many comparator, you need a
retirement unit to make the flot in the program sequence (you could even
add register renaming if you want).

But, how could it be possible to add more mips by clock cycle wihout all
that waisted ressources. Intel, Ti choose VLIW, AMD simd (as us). VLIW
add sometimes "false" parrallelism (duplicate code -> more code
space...) and make exeption very difficult to handle (wich slot have
failed ?). And SIMD aren't always possible. 

Then i have the idea to increase the number of acceded regiters. Break
the habit of 2 registers read and 1 write. For exemple, 4 read and one
write could be possible. It's much costly for the access to the register
bank and the instruction work should be wider but with the pipelined
software used to avoid bubble in the pipeline, a lot of registers are
used.

So we need more space in the instruction word, more access port in the
register and redesign all execution unit (but not really increasing
there latency).  

2IW (not VLIW) could be another good idea. We just manage the memory
beside usual instruction. We need a read register port, and 2 more bit
so a total of 8 bit in the instruction word.

There is 4 instructions : load/store/no operation/Sync. Memory load
could have a very large latency, so often it's better to do preload
(load data bevore you need them), so this part of the instruction are
decorelated from the other part(asynchrone system). When you absolutely
need a data, you just put a sync memory instruction, to finish all
current memory operation. There's nothing to change to unit because load
unit are present. Prefetch could be done with nop and a regiter != R0.

So we could break the 1.1 Vax Mips/Mhz of the Leon without having the
number of gate per Mips, too high.

But we should add a lock instruction to perform atomic operation to
manage a semaphore.

nicO
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/