Re: [f-cpu] parse VHDL code to create documentation

[Michael Strothjohann <strothjohann@rheinahrcampus.de>]

nicO schrieb:
> 
> It will be great to have a VHDL code parser that could generate in latex
> (?) graphic with input and output for the documentation (entity and
> FSM).

free VHDL-parsers are available, ( using bison i have written my own )
Generating a graphic block symbol from the entity in the vhdl-code is
not the problem. The FSM is somebit harder. There are different methodes
to describe a fsm in vhdl. Your VHDL2Graphic-converter has to be able 
to understand this methodes and *any* combination of them. 
Next you have to layout the position of the state-bubbles in your 
graphical output. ( with some hint from the user ?) I have just
seen a small progra ( written in java, sun-demo ), that is a good point
to start.
Are you interested ?   

> 
> It will create a document with each entity and all the input and output.

easy
 
> It will extracte the FSM to produice a graphics (it's much easy to
> debug).
> nicO

not so easy to write the FSM-VHDL->graphic converter 

michael strothjohann
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