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Rep:Re: Rep:Re: [f-cpu] parse VHDL code to create documentation



I'm very curious to see how renoir write hierarchical
FSM in vhdl. I have always a problem by missing each
time one cycle.

nicO
-----Message d'origine-----
De: Kim Enkovaara <kenkovaa@cc.hut.fi>
A: f-cpu@seul.org
Date: 27/06/01
Objet: Re: Rep:Re: [f-cpu] parse VHDL code to create
documentation

On Wed, 27 Jun 2001, Michael Strothjohann wrote:

> my opinion: please have in mind: fsms with more
then 10-15 states
> are easier to work with when there is a textural
(vhdl)-description,
> your display is probab not able to show all states
of your fsm at once. 

In good state machine tools (Renoir=HDL Designer)
there are no problems to
create hierarchical states etc. The graphical
reprsentation of FSM is very
intuitive for human reader and it's easy to notice
missing states etc.

After I really learned how to use the FSM tools I can
do state machine
much faster with them and with less errors. For
example SSDRAM control
state machine is quite complex, but I did the first
version in one hour
and it worked quite well.

=====================================================
========================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi |
Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            |
curved-space fault in
02630 Espoo         |                      |
write-only file system

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