Re: [f-cpu] manual update

[Michael Riepe <michael@stud.uni-hannover.de>]

On Sat, Jun 08, 2002 at 03:02:09AM +0200, Yann Guidon wrote:
> hi,
> 
> Michael Riepe wrote:
> 
> > On Thu, Jun 06, 2002 at 12:50:05PM +0000, Nicolas Boulay wrote:
> >> p195 Chapter 3
> > [...]
> >> - We can't impose that more than 2 register can't point on the same
> >> cache line. What happen with :
> > Why should we do that? Every register may point everywhere.
> 
> physically, yes.
> However there might be a HW limitation for the first versions.
> The code will work but might have some thrashing (one or
> two cycles of penalty per access where several pointers
> point to the same line).

I see.  In that case, the manual should read:

	`There may be hardware limitations that cause the F-CPU to run
	slower when more than two registers ...'

but not

	`... only two registers can point to the same cache line at a
	time, the four register must reference two different streams.'

which is simply wrong.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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