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[f-cpu] use of 1r1w regfile for our 3r2w regfile
- To: <f-cpu@seul.org>
- Subject: [f-cpu] use of 1r1w regfile for our 3r2w regfile
- From: <nico@seul.org>
- Date: Fri, 13 Jun 2003 17:11:54 +0200 (CEST)
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- Delivered-to: f-cpu@seul.org
- Delivery-date: Fri, 13 Jun 2003 11:12:03 -0400
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- Reply-to: f-cpu@seul.org
- Sender: owner-f-cpu@seul.org
To speed up regfile look up, we could use 4 1r1w regfile which introduice
4r4w port . In case of colliding, one clock cycle is lost.
My question is : Is that possible for the compiler to try to avoid such
bubble ?
nicO
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