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[f-cpu] vhdl code for R7
- To: f-cpu english ML <f-cpu@seul.org>
- Subject: [f-cpu] vhdl code for R7
- From: Etienne LABARRE <etienne.labarre@gadz.org>
- Date: Tue, 19 Mar 2002 22:36:00 +0100
- Delivered-To: archiver@seul.org
- Delivered-To: f-cpu-outgoing@seul.org
- Delivered-To: f-cpu@seul.org
- Delivery-Date: Tue, 19 Mar 2002 16:19:58 -0500
- Reply-To: f-cpu@seul.org
- Sender: owner-f-cpu@seul.org
- User-Agent: Mutt/1.3.25i
Hi all,
Excuse my poor english, it's not my first language (i'm french...)
I'm currently coding the register set (R7 unit) for the f-cpu. I sent
here my first version (with some YG remarks), and i whould like you to say your opinion.
It works with Simili and Vanilla, but it's not perfect. It's only a
valid model for simulation, and i think that we can perfect it.
For example, the 5-blocks organisation of R7 is
bit 00 to 07 = block 0 = 8 bits
bit 08 to 15 = block 1 = 8 bits
bit 16 to 31 = block 2 = 16 bits
bit 32 to 47 = block 3 = 16 bits
bit 48 to 63 = block 4 = 16 bits
This organisation has no signification for me today if
the registers aren't 64 bits wide. What's about if 128 bits ? add 4
16-bits blocks, or increase block width ?
I'm not in f-cpu team for long time, and i don't understand all the
subject...
Etienne LABARRE
r7_el.tar.gz