Re: [f-cpu] IEEE FP exceptions

[Yann Guidon <whygee@f-cpu.org>]

hi,

devik wrote:

> FYI (for nicO especially):
>
> While I was thinking whether FP precise traps are needed,
> I found article
> http://cch.loria.fr/documentation/IEEE754/ACM/hauser.pdf
> which describes pros and cons. He concludes that exceptions
> are not so needed (they are optional feature of standard)
> if you implement FPU status flags. There are better supported
> by languages and math librararies.
> For CPU designer it could mean possibility of impresise
> exceptions use because getfpflags() should act as FP instruction
> fence...
>  
interesting thought...

however the F-CPU has no "FPU status flag register".
It can be implemented as a SR (which is OK because
it enforces ordering of the instructions, good for future architectures)
and/or by a specific instruction that acts as a "fence" (ok too,
because it would then only serialize the FP pipeline in a split arch.)
And of course there is a condition code left,  we have
zero, LSB and MSB, and the remaining code can be assigned
to NaN or error condition, by reading a specific bit in the register
(so it's not the same as a "FPU status register", in the principle,
because there is no such thing as "sticky bits" and hacks like that).

hoping to revive this list,

> devik
>  
YG

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