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Re: [f-cpu] delayed issue



hi !

devik wrote:

http://www.ai.mit.edu/projects/aries/Documents/Memos/ARIES-06.pdf

VERY interesting reading !

almost in the same vein :

http://www.ai.mit.edu/projects/aries/Documents/Memos/ARIES-06.pdf

(don't look at the publication date too early)

well, now it explains a lot of things i've read on their project site....
they simply have fun with DARPA money.


Except for the "multistriped addressing" idea
( http://www.ai.mit.edu/projects/aries/Documents/Memos/ARIES-03.pdf )
i see nothing groundbreaking or worth caring.
They also explore some SMT (Simultaneous MultiThreading)
aspects in an interesting way but only in the beginning.
( http://www.ai.mit.edu/projects/aries/Documents/Memos/ARIES-07.pdf )

The rest is simply useless in a "classical general-purpose" processor.
Their ARIES architectures use straight Harvard (split address spaces for instructions
and data) which is not the best supported architecture under most OS
and compilers .... and they do only consider MPP (massively parallel computing)
while F-CPU shall be able to work as "standalone".
On top of that, it's highly object-oriented and their pointers are weird...

And here is a quote from
http://www.ai.mit.edu/projects/aries/Documents/Memos/ARIES-12.pdf :

The Hamal Instruction Set Architecture was
developed over a period of more than a year by a
process which can fairly be described as the worst
sort of engineering. It is almost purely the result of
thought experiments and hypothetical debates. With
the exception of some preliminary assembly
programming and scattered ties to existing
architectures, it has benefited from little to no realworld
validation.

However JPG got something right :

Simplicity also has advantages that silicon efficiency on its own
does not; simpler architectures are faster to design,
easier to test, less prone to errors and friendlier to
compilers.
This is why FC0 has no renamed registers, OOOE,
and other sophisticated control stuff.
Additionally, more complexity means more silicon area,
more dissipation, longer wires => more heat/dissipation,
more expensive and probably slower.
And control logic is certainly the least easy thing
to test in a chip. This is why i'm satisfied with
the current FC0.


-------------------------------
Martin Devera aka devik
Linux kernel QoS/HTB maintainer
http://luxik.cdi.cz/~devik/

YG

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