Re: [f-cpu] second order prefetch in FC0

[Yann Guidon <whygee@f-cpu.org>]

hi,

Martin Devera wrote:

> > > I understand. Maybe we could ask at comp.cpu.architecture as
> > > many people are there ...
> > >
> > >      
> > i can access to comp.arch but comp.cpu.architecture is unknown in my
> > server :-/
> >    
> sorry I mean .arch. I never remember the names.
>  
heh, "comp.arch" is simple enough to remember it :-P

> > > I found some citations about multi-prefetch techniques so that
> > > maybe it is/was unpatentable prior art.
> > what is multiprefetch ?
> > is it several interleaved prefetches ?
> >    
> it is generaly technique to prefetch along multiple
> pointer paths. Like to prefetch both pre and next item
> along with main item. Or two prev & next.
> If DEC patented its use inside of cachelines we could go
> by suppoorting sw multi prefetch by some insn.
> It should be tested in gcc first of course.
>
> By the way, when we describe the idea here, can it be
> taken as prior art ? So nobody can patent it ?
>  
in theory, ....
and in practice ....

you can't be sure because lawyers are masters at bendind
reality and our subject is a dangerous minefield.
It's why F-CPU is more secure than OpenRISC because
Damjan & Co. have based their architecture on MIPS,
while F-CPU is completely unrelated (this answers to
another mail) so there are less risks to come across
their patents.

> devik
YG


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