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[f-cpu] Register set revised



Hi,

sorry for opening this again. While working on other
project we discovered other possibilty of register set.
First, it would assume 2r2w set. I know some don't
like it but I think too that 3r is unnecessary
(MAC with 4 cycle latency is questionable for pipelning,
 store with postincrement usually works with immediates
 only, MUX is rarely used and simple to do with andn).

I modified GCC to handle split set of two 1r1w
register sets. Each binary op can use one operand
from set A and one from B.
Pointers are only in B. Calling convention places
pointers to B and others to A.
I've done it in testing mode for binary ops and
stores and it seems that 70% of ops are ok.
When we will spend more time on it I believe that
we can reach about 90%.
Mis-placed read will have 1 cycle penalty needed
for second read. Writes can be to any bank - compiler
should attempt to store results so that banks
are interleaved (whenever possible for commutative ops).
One could also disable cross-split reads and change
6 bit read register id to 5 bit (writes are still 6bit).

Such split set would be both simpler and faster. And
because of many comutative ops ("add" is most used)
it can be expected no big penalty will occur.

Just idea ....

-------------------------------
    Martin Devera aka devik
  http://luxik.cdi.cz/~devik/

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