Re: [f-cpu] New VHDL Stuff - Xilinx synteheis report

[Michael Riepe <michael@stud.uni-hannover.de>]

On Sun, Mar 30, 2003 at 05:44:47PM +0200, Yann Guidon wrote:
[...]
> >ASU: 601 slices, 69 MHz
> >MUL: out of memory (have only 150MB swap in vmware)
> >SHL: recursion detected in 'shift_map'
> >INC: many messages like
> >       Signal <a59<34>> is used but never assigned. Tied to value 0.
> >       WARNING:Xst:821 - C:/xilinx_webpack/ISEexamples/fcpu/bit_manipulation.vhd
> >         (Line 269). Loop body will iterate zero times
> >     258 slices, 128 MHz but I expect problems here
> >CMP the same.
[...]
> at least the ASU works ;-D

Don't worry, it's not a big deal -- just the old "brain-dead synthesizer"
problem again that forces me to uglify my code.  And EU_IMU simply is too
big for 150 MB (and for that tiny Xilinx Spartan FPGA) -- Synopsys/SPARC
needed 1 GB of RAM to synthesize the previous version.

I already sent a patch that may fix the other units, and I'll re-release
the whole package once it works.  Should be only a matter of days.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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