Re: [f-cpu] asynchronous circuits

[Yann Guidon <whygee@xxxxxxxxx>]

hi,

woodelf wrote:

> Well this boils down to gate level logic, somthing that has to be faced
> regardless of the abstract views used. From what little I have have seen
> with modern CMOS logic power comsumption is used more for driving long 
> lines* rather than clocking, and the problem will get worse in the 
> future. The logic design needed is logic that is compact logic since 
> most of the logic designs have been developed already. Finding the non
> -patented ones may be hard.
> Note a long line may be 10 gates distant away since wire capactance is
> geting larger than the gate capactance of the CMOS gates.

- concerning the patented designs : well, there is so much prior art for 
basic things ...
- concerning long lines : that's going to plague FC0, sure. some time 
ago, i thought it would be the register set....
Now, the Cell's CPUs have really large register sets and run /fast/.
And tomorrow, it is going to be something else that slows it all.
well, we would be able to measure all this if
- we had a complete source code
- we had synthesis/place/route SW...
both are very difficult to obtain, btw ;-)
YG

/away for some days again

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