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Re: [f-cpu] Really cheap FCore prototyping...



Nikolay Dimitrov wrote:
Dear all,

Several days I was thinking about the YG thoughts (as I recalled) "... it doesn't matter how fast it is, it does matter that it is free...", I found an interesting solution.
There are several software simulators for the FCore, but what do you say for a real HARDWARE simulator? No, don't scream, I don't mean FPGA. It's not (very) cheap, and tools are complicated. But how can one deploy the core on a hardware, without millions of dollars, or even a FPGA? There is a very cheap programmable logic, all around the world, called microcontrollers. PIC, AVR, Atmel ARM7, just name a cheap and fast RISC! To the chip can be connected some SRAM memory to extend the data storage of smaller controllers to hold enough "registers" of the emulated core. I recall - it won't be fast, but this is unique way to CREATE NOW working prototypes of our favourite core! Just imagine - portable prototypes of FCpu hanging in your pocket, working with a 3V LiIon batt, drawing about 5-15mA, and achieving 0.1 - 1 MIPS ?

These times I'm thinking in similar way. Because I've several ideas (some already expressed here) but these must be proven. The correct way IMHO is to simulate the device (I can't find any fc0 architectural cycle precise simulator - does it exist ?).
The problem is that I can imagine ISA simulator running with 10-50 times slowdown (maybe 50 MIPS on my PC) using basic block translation into simulator host's machine code.
But typical slowdown for architectural cycle precise simulators is about 10.000 (SimpleScalar) or 5.000 (FastSim).
So that I expect simulation at 200 kIPS on my machine.


What I'm really interested in is how much performance lies in 3r2w register set vs 2r1w, in various types of LSU etc.
SimpleScalar simulator allows you to create whole cpu simulator with working libc and syscalls translated to host's syscalls. Thus you can run real benchmarks.


What distracts me from f-cpu project is that creating (even free) cpu which is outperformed in all ways by other chips is not so funny. Even whining why don't add this and that feature is pointless if you can't measure it.
So that I plan to try simple scalar and create very simple fcpu like
device with FMT a play with the architecture and measure its performance.
Maybe I'll find that is lags so much in performance that I'll stop thinking about it. Maybe I find so interesting numbers that it ignites more exitation about it ;-)


devik
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