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[f-cpu] accelerator
- To: f-cpu@seul.org
- Subject: [f-cpu] accelerator
- From: Graham Seaman <graham@seul.org>
- Date: Tue, 14 May 2002 13:11:39 -0400 (EDT)
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- Delivered-To: f-cpu@seul.org
- Delivery-Date: Tue, 14 May 2002 13:11:39 -0400
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http://www10.edatoolscafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=30886
Anyone know how this works? Does it compile bits of a design to FPGA and
read back the results to merge with the software simulation?
Graham
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