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Re: [f-cpu] Shifter, like during the good old days ;p



hi,

nicO wrote:
> ------
> elaborate Shuffle64 -gate_clock
> Error: Can't determine type of aggregate or concat
>         in routine rotate line 181 in file
> '/home/profelec/nboulay/perso/fcpu/shl/fcpu-shl-mr-20
> 011102/eu_shl/shuffle64.vhdl'
>         called from Shuffle64 line 312 in file
> '/home/profelec/nboulay/perso/fcpu/shl/fcpu-shl-m
> r-20011102/eu_shl/shuffle64.vhdl' (HDL-123)
> No designs were read
> 0
> --------

thank you :-D

> nicO
> 
> Michael Riepe a écrit :
> >
> > Hi!
> >
> > Here's another version of the shifter.  It now uses a 6-stage omega
> > network (in fact, a *reversed* omega network) for bitwise operations.

i don't understand what this means.
is a drawing available ?

> > Additional changes:
> >         - cleaner, more regular code
this helps ;-)

> >         - since the core is basically a rotate unit, shifts are now
> >           performed by `rotate-and-mask'. A second output holds the bits
> >           that were lost, giving us `double' shifts for free (but only
> >           the 2r2w ones; 3r1w double shifts are not supported).
that's cool enough.

> >         - as a consequence of the implementation, `bitrev' now has a
> >           SIMD counterpart, `sbitrev'. `bitrevo' isn't supported.
ok.

> >         - performs both mixl and mixh (or expandl and expandh) at
> >           the same time (2r2w).
> >         - can perform either byterev or sdup on two independent
> >           input operands (2r2w).
great !

i'd like to see a "textual" architectural description.
The choice of an omega network looks curious to me.

> > I didn't test all extensions; I'd like to see synthesis reports before
> > I go on (maybe this is even slower than the last one).
you have nicO's answer :-)

btw, i'm currently trying to (re)write some C code using the Xlib.
i search a way to bypass the window manager when the user enters
ALT + mouse button/drag ...

> >  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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