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Re: [f-cpu] FC0 P&R : i finally got it !



hello,

Kim Enkovaara wrote:
> 
> On Sun, 11 Nov 2001, Yann Guidon wrote:
> 
> > The next step is cool : given enough metal layers are present,
> > we can draw vertical wires to feed the multiply unit, located
> > "above" (from the upper side point of view) the other units and
> > register set. Because this unit is long  and has several outputs,
> > vertical wires will be drawn wherever needed and meet the
> > horizontal main buses. i have no patience or skill to draw
> > that with ASCII stuffs but it seems to work on paper sketches.
> 
> Have you tought about crosstalk problems? At least big bunch of vertical
> lines can be a problem unless you add extra wires that are grounded etc.
> This will not be a big problem at 0.18, but is beginning to be a real
> problem at 0.13. There are tools to analyze the crosstalk and fix the
> problems at layout, but they are very expensive tools.

Of course, Xtalk is a big problem. i don't know a lot about it and
i think that it is not a concern where i study (they have enough problems
programming their own dumb P&R...). However, we will certainly have
to do whatever is necessary (in the case where manual placement is done)
and i don't think that extra grounded wires are too much.
Btw, the vertical Xbar wires are only used to communicate with the
multiplier so the wire density (for this part) is not too high.

ok, now i have to finish the optimisation of the datapath of the
f*ck*d *p microcoded MIPS for the university project. the kind of stuff where the
critical datapath makes big zig-zags across the whole circuit :-(
a first timing analysis for .35u gave 17MHz for the core and 3MHz with the pads :
they "only" forgot to buffer the clock signal... now i have to redesign their
add/sub unit using precharacterized 4-bit add blocks instead of their
dumb 32-bit long carry chain.

> =============================================================================
> Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
WHYGEE
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