Re: [f-cpu] whygee's Nth slaughtered ROP2 version

[Yann Guidon <whygee@f-cpu.org>]

hello,

Josh Fender wrote:
> On Sun, 25 Nov 2001, Michael Riepe wrote:
> > On Sun, Nov 25, 2001 at 03:47:12AM +0100, Yann Guidon wrote:
> > [...]
> > I guess 85 MHz in an FPGA is not bad (depends on the FPGA type, of
> > course).  I'd like to see the numbers for the add, mul and shl units,
> > too (for the same target, as far as possible -- the multiplier probably
> > won't fit, but the other EUs should).
>   If someone was to provide a working set of units, I could try them all
> out.  I could try the multiplier unit aswell as the FPGAs I am using are
> relatively large (approximately 40000 Look up tables/ Flip Flops units).
> It might not fit but its always worth a try.

thank you !

>   I am curious about the target of the F-CPU.  A lot of the design seems
> to be oriented towards FPGAs and their four input logic, yet the
> multiplier most certainly is not.  So my question simply is:  What is the
> current target platform for the first F-CPU?  Is it an FPGA or a custom
> chip.

concerning the "target", it ranges from SRAM-based FPGA to semi-custom,
depending on what tools are available. Of course if we wanted to compete
with Intel, full-custom teams would have to work, but let's be realistic :-)
but whatever step in any direction is apreciated.
I hope it is not too fuzzy :-)

> - Josh
WHYGEE
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