Re: Re: [f-cpu] New suggestion about call convention

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

Hummm some explanations can be required.

storem r16,[sp],r31 can be seen as equivalent of :

store r16,[sp]+
store r17,[sp]+
...
store r13,[sp]

so loadm r16,[sp],r31 :

load [sp]-,r31
load [sp]-,r30
...
load [sp],r16

How does storem r1,[r2],r3 work :

1) store the value of r1 at memory [r2]
2) if r1 and r3 has the same register number, stop here and let the next
instruction to run
3) increase the register number of r1 in the instrution format
4) increase the address stored into r2
5) rexecute the modified instruction or insert it as a next instruction in
instruction queue
How does loadm r1,[r2],r3 work :

1) load the value at memory [r2] into r3
2) if r1 and r3 has the same register number, stop here and let the next
instruction to run
3) decrease the register number of r3 in the instrution format
4) decrease the address stored into r2
5) rexecute the modified instruction or insert it as a next instruction in
instruction queue

Note : I'm not sure about load operation, source register is first operand
or third operand ? using third operand would share more things between load
and store operations.

Non trivial parts are 3 and 5.

Number of generated "instructions" is n where n = register_index(r3) -
register_index(r1).

maskstore mr,[sp],r16 (mr is ...101x) :

                                 : store r16,[sp]+
lsb(mr = ...0101) = 1 : store r17,[sp]+
lsb(mr = ...0010) = 0 :
lsb(mr = ...0001) = 1 : store r19,[sp]
...

maskload mr,[r1],r16 (mr is ...101x) :

                                 : load [r1]+,r16
lsb(mr = ...0101) = 1 : load [r1]+,r17
lsb(mr = ...0010) = 0 :
lsb(mr = ...0001) = 1 : load [r1],r19
...

How does maskstore r1,[r2],r3 work :

1) store the value of r3 at memory [r2]
2) while lsb(r1) is 0 and r1 not 0, increase the register number of r3 in
the instrution format and right shift r1.
3) check if mask r1 is 0, if so stop it and let the next instruction to run
4) increase the address stored into r2
5) rexecute the modified instruction or insert it as a next instruction in
instruction queue

How does maskload r1,[r2],r3 work :

1) load the value at memory [r2] into r3
2) while lsb(r1) is 0 and r1 not 0, increase the register number of r3 in
the instrution format and right shift r1.
3) check if mask r1 is 0, if so stop it and let the next instruction to run
4) increase the address stored into r2
5) rexecute the modified instruction or insert it as a next instruction in
instruction queue

Non trivial parts are 2 and 5.

Number of generated "instructions" is n where n = number of bits set to 1 in
r1 except for the lsb which is always counted as 1.

Conclusion :

well, such a solution have some drawbacks :

- if an resumable exception occurs, we need to keep the modified instruction
so we can be able to resume from it and not from the original instruction.
- a more complex scheduler to handle instruction self-modification, not
speaking about the difficulties for pipelines.
- a more complex instruction decoder able to handle instruction
self-modification.

You know what ? I think it will always be a nightmare to have a great CPU
without any sacrifices :((( (I mean whatever the side is)

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