Re: [f-cpu] pointer add & sub

[Yann Guidon <whygee@f-cpu.org>]

hi,

Antoine wrote:

>>>You could have the following :
>>>
>>>- add r3,r2,r1 => r1.pointer = r2.pointer XOR r3.pointer
>>>- sub r3,r2,r1 => r1.pointer = r3.pointer AND NOT r2.pointer
>>>
>>>(as for immediates, the obvious convention is imm8.pointer = false)
>>>
>>>So, unless there are useful exceptions to the above,
>>>you can get rid of special "memory pointer" operations.
>>>      
>>>
>>In fact a pointer imply a TLB check, so it complicate really a lot the normal 
>>adder. In F-CPU it's more logical to add a new instruction that only with 
>>memory.
>>    
>>
>
>That doesn't mean you need to have two different opcodes !
>
madd needs no saturation, SIMD or whatever.
but if madd is a subset of add, it has another function
and there is no room left in the opcode....

>(by the way, what is the current opcode count ? the max is 256...)
>
are we still around 110 ?

>Also, the TLB check is speculative and performed after the addition
>so it needn't be in the main execution path, does it ? So I don't  
>understand why the adder in itself would be complicated by this.
>  
>
the adder itself is not changed.

however, checking ALL results from Xbar in the TLB (just as the "zero 
check" does)
consumes more resources and power. By only "activating" the TLB when needed,
this part consumes less power.

>My feeling was that madd/msub had been added because people
>didn't know how to calculate the pointer flag after a normal
>arithmetic operation...
>  
>
The pointer flag is nothing. The "valid" flag is more important.

FYI :

There are two flags (on top of the zero and some for SRB when/if 
implemented) :
 - "pointer flag"
 - "pointer valid flag".
And this is "only a model", as the implementation can differ (for example
with some associative memory instead of 1 flag per register).

when "pointer flag" is unset AND a load/store is required,
then a "penalty cycle" (several cycles in fact) is necessary
to "refresh" the flag.

when it is set, "pointer valid" indicated whether to trap or continue.

An additional flag is necessary to distinguish between data and
instruction, but it can also be implemented as a set of 2 separate
associative memory blocks.

Another rule is that after any operation, the register's "pointer" flag
is cleared (or the entry is removed from the CAM). This is to
prevent any case of protection violation or race conditions or whatever.
So if a "normal" operation updates a register which then used as a pointer,
the TLB must be rechecked. Only the post-incremented instructions
do update the "pointer valid" flag (after it has been reset, like with 
any other
instructions) because it's the most common case. The loopentry/prefetch
family of instructions also "copy" the pointer flags.

YG

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